Finfet architecture analysis and fabrication mechanism. He was the founding chairman of celestry design technologies, an ic design software company that was acquired by. The industry is converging on 7nm finfet as the next longlived node. Finfet based design for robust nanoscale sram prof. Chenming group is the first to have finance companies and financial leasing companies in paper industry, the only listed company to have a, b and h shares in china, and is rated as one of the 50 most cpmpetetive blue chip company in china. He is tsmc distinguished professor emeritus in the electronic engineering and computer science department of the university of california, berkeley, in the united states. Chenming hu, the 2020 ieee medal of honor recipient nhl season could resume with fourarena plan, commissioner bettman says saskatchewan to outline plan for gradual restart to economy beginning next month.
This book is the first to explain finfet modeling for ic simulation and the industry standard bsimcmg describing the rush in demand for advancing the technology from planar to 3d architecture, as now enabled by the approved industry standard. Thin fin and gate can be made with the same lithography and etching tools. Physics and modeling of finfet and utbsoi mosfets using bsimmg as example. Either we have a crash program to work it a materials solution out or we substitute novel device structures such as finfets. He has received the us national medal of technology and innovation from president barack obama and uc bekeleys distinguished teaching award. He has received the us national medal of technology and.
Some of the key process challenges in creating finfet structures. Chenming hu, tsmc distinguished professor at uc berkeley. In this article, key elements that differentiate junctionisolated bulk and dielectricisolated soi finfet transistors are discussed, encompassing aspects of process integration, device design, reliability, and product performance. Finfet a selfaligned doublegate mosfet scalable to. For now, gateallaround technology appears to be the most practical technology after finfets. A lateral gateallaround technology is basically a finfet on its side with a gate wrapped around it. Bora nikoli zheng guo, sriram balasubramanian, andrew carlson, radu zlatanovici 2 outline background motivation finfet based sram cell designs. Chenming calvin hu s seminal work on mos reliability and device modeling has had enormous impact on the continued scaling of electronic devices, enabling smaller yet more functional and higherperformance integrated circuits.
Cmosbased electronics will remain vital for a century or more, according to dr chenming hu, widely regarded as the father of the finfet transistor architecture to which the semiconductor industry is currently transitioning. This cited by count includes citations to the following articles in scholar. Jul 11, 2016 finfet is a transistor design first developed by chenming hu and his colleagues at the university of california at berkeley, which tries to overcome the worst types of sceshort channel effect. Finfet layout layout is similar to that of conventional planar mosfet, except that the channel width is quantized. Basis for a finfet is a lightly pdoped substrate with a hard mask on top e.
In a 22 nm process the width of the fins might be 10. Technology and manufacturing day intel technology and manufacturing day 2017 occurs during intels quiet period, before intel announces its 2017 first quarter financial and operating results. Chenming group, chenming paper shandong chenming paper. Chenming hu joined the faculty of the university of california, berkeley, in 1976 top. Pdf finfet modeling for ic simulation and design using. Finfet is a promising device structure for scaled cmos logicmemory applications in 22nm technology and beyond, thanks to its good short channel effect sce controllability and its small variability. Finfet is proposed to overcome the short channel effects.
The origins of intels new transistor, and its future. The finfet architecture has helped extend moores law, with designs currently stretching to the 10 nm technology node. Mosfet structure and its particular type named as finfet technology and its. As in earlier, planar designs, it is built on an soi silicon on insulator substrate.
Jae king liu department of electrical engineering and computer sciences university of california, berkeley, ca 94720. Internal view of a soi finfet showing the fin and b poly gate wrapping around the fin this work focuses on the implementation of a complete process flow of 22nm triple gate soi finfet into a commercially available numerical 3d process and device simulation environment. Pdf modern semiconductor devices for integrated circuits. Another important consideration is whether the technology is provenhave others already made the switch and how reliable is the technology. Finfet is a beginning chenming hu university of california berkeley. Finfet 3d transistor photo archive paintings by chenming hu paintings by raymond hu. Intel will use 3d finfet at 22nm most radical change in 4 decades there is a competing soi technology chenming hu, march 20 2. Construction of a finfet fundamentals semiconductor. Therefore, presenters will not be addressing first quarter information during this years program. Modern semiconductor devices for integrated circuits chenming calvin hu student solution manual rapi download. Interview of chenming hu at uc berkeley on finfet, innovation, and the semiconductor industry in 2015 when all top android and ios cell phones started using finfet processors. Figure 1 structure of finfet 2 3 silicon on insulator soi process is used to fabricate finfet. Finfet a selfaligned doublegate mosfet scalable to 20 nm.
With customers taping out now and getting ready for volume production on finfet processes from leading foundries, its not a risky choice to use one of the many finfet process for your next design. Chenming hu is the tsmc distinguished chair professor of electrical engineering and computer sciences at uc berkeley. Chenming has been awarded successively over 200 honorary titles at the provincial level or above. All content in this area was uploaded by chenming hu on may. Soi finfet with thick oxide on top of fin are called doublegate and those. Jin he, jane xi, mansun chan, hui wan, mohan dunga, babak heydari, ali m.
Is finfet process the right choice for your next soc. Finfet becomes attractive due to its quasiplanar structure, better immunity to sces, range of channel lengths, cmos compatibility, good area ef. Obama presents national medal to chenming hu president obama presents the national medal of technology and innovation to chenming hu on may 19, 2016. Modern semiconductor devices for ics free download as powerpoint presentation. Since there is no stop layer on a bulk wafer as it is in soi, the etch process has to be time based. The altered mass is called e ective mass, mn and mp 4. The band model is the tool required for quantitative analysis of semiconductors. Feb 15, 2018 finfet, also known as fin field effect transistor, is a type of nonplanar or 3d transistor used in the design of modern processors.
Nanoscale cmos spacer finfet for the terabit era ieee. Integrated circuit scaling to 10 nm and beyond mark bohr, intel senior fellow. Based on this, finfets with one atomic layer fin are obtained, with onoff ratios reaching. A fin fieldeffect transistor finfet is a multigate device, a mosfet built on a substrate where.
While that is an amazing achievement, the industry is already working on ways to continue transistor scaling. Their mass however is altered from the mass of an electron in vacuum. Intel is the first company to use finfet in 2011 production calling it the most radical shift in semiconductor technology in over 50 years. Design and implementation author jamil kawa synopsys fellow introduction four years following the introduction of the first generation finfets, the 22nm trigate, and roughly one year after the first production shipments of 1416nm finfets, 10nm finfet designs are taping out and are slated for production in 2016. From 2001 to 2004, he was the chief technology officer of tsmc. He is a professor with the graduate school of uc berkeley and a board director of sandisk corp. Modern semiconductor devices for integrated circuits. In 2009, the institute of electrical and electronics engineers.
A fin fieldeffect transistor finfet is a multigate device, a mosfet metaloxidesemiconductor fieldeffect transistor built on a substrate where the gate is placed on two, three, or four sides of the channel or wrapped around the channel, forming a double gate structure. Simulationbased study of supersteep retrograde doped bulk. That is a limitation of finfet, and this is called width quantization. The team made the following breakthroughs between 1998 and 2004.
Charles kuo, erik anderson, tsujae king, jeffrey bokor, fellow, ieee, and chenming hu, fellow, ieee. Figure 1 depicts the geometry of finfet being simulated. Using the bsimcmg standard chauhan, yogesh singh, lu, darsen duane, sriramkumar, vanugopalan, khandelwal, sourabh, duarte, juan pablo, payvadosi, navid, niknejad, ai, hu, chenming on. From 2d simulation of dg finfet, it is found that the gatelength. Sep 03, 2011 finfetwhat it is and does for ic products, history and future scaling 20110805. National institute of advanced industrial science and technology multigate finfets s g d 1st finfet patent in 1980 from aist finfet proposed by aist in 1980 named finfet by ucb in 1999.
His early research at berkeley included hybrid cars, like the gas. We survey different types of finfets, various possible finfet asymmetries and their impact, and novel logiclevel and architecturelevel tradeoffs offered by finfets. Alternatively, in the singlegatemode, one gate is biased with the input signal while the other gate is. History of finfet finfet is a transistor design first developed by chenming hu and his colleagues at the university of california at berkeley, which tries to overcome the worst types of sceshort channel effect. Lu sriramkumar venugopalan sourabh khandelwal chenming hu. The ones marked may be different from the article in the profile.
Finfet and other new transistor technologies chenming hu univ. Solutionmanualformodernsemiconductordevicesforintegratedcircuits chenming c. Abstract finfet devices are comprehensively investigated owing to the projection for application in the cmos integrated circuits fabrication. Chenming hu, august 2011 11 finfet leakage path s d. What may happen finfet will be used at 22nm by intel and later by more firms through and beyond 10nm. Tsu jae king, chunghsun lin, mohan dunga, angada sachid, sriram v. Finfet modeling for ic simulation and design elsevier scitech connect. Finfet general mosfet at submicron level is suffering from several submicron issues like short channel effects, threshold voltage variation etc.
Simulationbased study of supersteep retrograde doped bulk finfet technology and 6tsram yield by xi zhang research project submitted to the department of electrical engineering and computer sciences, university of california at berkeley, in partial satisfaction of the requirements for the degree of master of science, plan ii. Apr 18, 2015 finfet is a transistor design first developed by chenming hu and his colleagues at the university of california at berkeley, which tries to overcome the worst types of sceshort channel effect. Sep 16, 2016 globalfoundries announces new 7nm finfet process, full node shrink. He was formerly chief technology officer of tsmc and is best known for contributions to ic reliability, bsim spice models, and the finfet transistor. Quantummechanical confinement and double junctions in finfets. Chenming hu books list of books by author chenming hu. Finfet what it is and does for ic products, history and future scaling 20110805. Bulksi mosfet source drain source gate gate source drain source finfet w eff 2 h fin n fins n gatefingers fin pitch p fin is a new key parameter to be optimized for performance and layout efficiency. Finfeta selfaligned doublegate mosfet scalable to 20 nm digh hisamoto, member, ieee, wenchin lee, jakub kedzierski, hideki takeuchi, kazuya asano, member, ieee, charles kuo, erik anderson, tsujae king, jeffrey bokor, fellow, ieee, and chenming hu, fellow, ieee abstract mosfets with gate length down to 17 nm are reported.
Finfet modeling for ic simulation and design using the bsimcmg standard april 2018 yogesh singh chauhan d. By 2015 all top servers, computers, android and ios phones use finfet. One of the many interesting topics in the new 3d finfet technology is the approach to isolation. Chenming hu, tsujae kingliu and jeffrey bokor at the university of california, berkeley who were the first to coin the term as a result of the shape of the structure. Semantic scholar profile for chenming hu, with 124 highly influential citations and 86 scientific research papers. Chenming hu has been called the father of 3d transistor for developing the finfet in 1999. Ensure your research is discoverable on semantic scholar. Chenming paper chinese painting handmade paper chen ming hsien enjoy modern painting modern painting by the chinese society for the study of modern chinese painting director. From this model one can get the energy gap, ek diagrams allowing the determination of e ective masses. Electrons and holes are the major characters in the play and carry opposite charge.
Finfet interview of chenming hu at uc berkeley on finfet, innovation, and the semiconductor industry in 2015 when all top android. Pdf a simplified fabrication process for sub20 nm cmos doublegate finfets is reported. Now you can create the design by using the finfet symbols by pressing i in schematic. Finfet technology takes its name from the fact that the fet structure used looks like a set of fins when viewed. Globalfoundries announces new 7nm finfet process, full node. Finfet what it is and does for ic products, history and future scaling by narlndl. Professor emeritus, professor in the graduate school. Its an evolutionary step from finfets and shares many of the same process steps and tools.
He and his team published seminal papers on finfets 1999 and utbsoi 2000. Niknejad, chenming hu, chargebased core and the model architecture of bsim5, proceedings of the sixth international symposium on quality of electronic design isqed05, pp. Thats partly what i meant about using threedimensional devices referring to his comments during a panel discussion on getting. Cmos good for another century, says father of finfet. An independentgate finfet ig finfet provides two different active modes of operation with significantly different current characteristics determined by the bias conditions. Jun 10, 2016 interview of chenming hu at uc berkeley on finfet, innovation, and the semiconductor industry in 2015 when all top android and ios cell phones started using finfet processors. Chenming hu engineering and technology history wiki. The fins are formed in a highly anisotropic etch process.
This post first appeared as part of the advanced substrate news special edition on fdsoi industrialization. The group was led by hisamoto along with tsmcs chenming hu. This book is the first to explain finfet modeling for ic simulation and the industry. Finfet modeling for ic simulation and design 1st edition. Fabrication and characterization of bulk finfets for future.